The present application relates generally to a delay circuit, and more particularly to a variable delay circuit having one or more delay elements that are configured for low power operations in a high integration environment.
A delay circuit in a semiconductor device controls the output timing of an input signal such that the inputted signal is outputted after a predetermined delay as an output signal of the delay circuit. In digital circuitry, multiple digital signals could be simultaneously inputted for processing, but the order according to which these inputted multiple signals should be made available for processing must be controlled in order to produce appropriate signals (e.g., control signals, data signals, etc.) at the appropriate timings or intervals in order to perform properly the required operations demanded by the digital circuitry. In general, a signal delay in a synchronous circuit that is synchronized to an external clock is measured in terms of the number of delayed clock cycles, and this is generally referred to as the latency of a signal. In this regard, a delay circuit controls the latency of an inputted signal.
For example, a conventional delay circuit controls the signal latency using a predetermined number of shift registers: SR1, SR2, SR3, . . . SR(n−1), SR(n) that are serially connected, and the operation of these serially connected shift registers is synchronously controlled by a clock signal. Each of the shift registers is designed to provide one-clock cycle delay. Thus, an input signal inputted to the series of shift registers SR1 to SR(n) would provide n number of delayed output signals L1 to L(n) at each output of the shift registers SR1 to SR(n). Then, any one of the n number of delayed signals L1 to L(n) can be chosen for the delayed output signal.
However, there are numerous problems associated with the conventional delay circuit. For example, if any of 0-16 clock cycle delays is desired, then 16 units of serially connected shift registers SR1 to SR16 would be required. From each of the shift registers, the delayed signals L0, L1, L2, L3, . . . L16 would be produced at each stage of the delay elements SR1 to SR16. Any one of the delayed signal L0 to L16 are available to be chosen to meet the need of the delayed circuit operation.
This means that a conventional delay circuit would require a total of “n” number of shift registers for a latency control of anywhere from 0 to “n” clock cycles. The number of shift registers is therefore determined by the maximum latency sought, and, this means that the size of the selection circuit (such as a multiplexer) needed for selecting one of the n number of delayed signals (i.e., L0 to L(n)) will inevitably be undesirably large as the number of shift register increases to realize a longer latency. This is very counterintuitive to high integration device sought by the modern circuit design.
For a larger latency “n,” the number of signals L0 to L(n) inputted to the selection circuit such as a multiplexer will increase, and the parasitic resistance and capacitance associated with signals inputted to and outputted from the multiplexer will also increase. Additional buffers will be necessary in order to resolve the problems of parasitic resistance and capacitance, which in turn will demand undesirably increased power consumption and increased circuitry size.
The selection circuit or a multiplexer will respond to a selection signal such as SEL<0:n> in order to determine which one of the delay signals, for example L0 to L(n), should be outputted. The size of a decoder required for producing the multiplexer control signal S<0:n> will also inevitably increase for a larger latency “n.” For example, the size of a decoder will double for each one-clock cycle increase in latency. Not only the size but also the electrical energy consumption increases since all of the “n” number of delay elements or the shift registers in the circuit needed for controlling the latency for 0 to “n” clock cycles must be turned on at all times.
Further, the latency required increases with the ever-increasing clock frequency implemented in the ever-advancing modern digital circuitry, which is more complex and designed to perform more and more of many different system functions. In order to perform more number of system functions, it will require more number of circuits needed to perform the required functions. This will in turn require more number of larger-size delay circuits in order to control the signal timing of the input/output signals utilized the increased number of circuits. This will cause the electrical power consumption to increase, which is counterintuitive to the low power requirement sought by the modern circuit design.